http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I718629-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-017 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03C3-0991 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03C3-0966 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-07 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-1565 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-0231 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-0315 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-135 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03C3-09 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-07 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-08 |
| filingDate | 2019-08-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2dcf53189ab0e00c587384e1d8392b33 |
| publicationDate | 2021-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-I718629-B |
| titleOfInvention | Clock circuit, clock duty cycle adjustment and calibration circuit and method of operating same |
| abstract | A clock circuit includes a set of level shifters, an adjustment circuit nand a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle, and is coupled to the adjustment circuit. The adjustment circuit is configured to generate a first clock output signal responsive to a first phase clock signal and a second phase clock signal of the first set of phase clock signals, and adjust the first clock output signal and a second duty cycle of the first clock output signal responsive to a set of control signals. The calibration circuit is coupled to the adjustment circuit, nand configured to perform a duty cycle calibration of the second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I781008-B |
| priorityDate | 2018-08-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 44.