| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_690aecc98f0c1b2f102e4874d5dae33d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1464
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14627
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14625
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-16235 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14632
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5384
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5386
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14687
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14698
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14618
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3107 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48 |
| filingDate |
2019-09-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_00b6b63dd7c3d2bbe4a8b78d07d6b3c4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_17df7989b242b18c9827de3bf119a7fc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a770138ffff08fb32408619b04e675d5 |
| publicationDate |
2021-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I717846-B |
| titleOfInvention |
Chip package and method for forming the same |
| abstract |
A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite to the first surface, and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device therein and adjacent to the first surface. The first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. The electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending between the second surface of the substrate and the second conductive portion from the first isolation portion. |
| priorityDate |
2018-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |