| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fa907cbef2178b7f30a042518be6b17b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02595
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0262
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02667
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28568
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53271 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-324
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8239 |
| filingDate |
2018-08-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6b98a67594be1a7f27cacb9959e903ee
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a36af7e4740704da8623859b29a7da4b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0b8d98e9a04cd9aa8ba6cde1d3f8117b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1fcf986dda982bc8146170e7e14e182e |
| publicationDate |
2020-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I692841-B |
| titleOfInvention |
Array common source structure of three-dimensional memory device and its forming method |
| abstract |
A method for forming a 3D memory device is disclosed. The method comprises: forming an alternating conductive/dielectric stack on a substrate; forming a silt vertically penetrating the alternating conductive/dielectric stack; forming an isolation layer on a sidewall of the silt; forming a first conductive layer covering the isolation layer; performing a plasma treatment followed by a first doping process to the first conductive layer; forming a second conductive layer covering the first conductive and filling the slit; performing a second doping process followed by a rapid thermal crystallization process to the second conductive layer; removing an upper portion of the first conductive layer and the second conductive layer to form a recess in the slit; and forming a third conductive layer in the recess. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I776230-B |
| priorityDate |
2017-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |