Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fa907cbef2178b7f30a042518be6b17b |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-80896 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-80895 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-24 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66757 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42384 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-063 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7926 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11551 |
filingDate |
2018-11-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2020-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6455ef9534411f318d701984a127dc95 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0b8d98e9a04cd9aa8ba6cde1d3f8117b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_df5f88da2be024d65cef4de08b841e5f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8865aec9b278a970809af7010c2c6ed4 |
publicationDate |
2020-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
TW-I685953-B |
titleOfInvention |
Memory device using comb-like routing structure for reduced metal line loading |
abstract |
A memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and one or more peripheral device on the first substrate. The second semiconductor structure includes first group conductive lines electrically coupling to a first group of multiple vertical structures and second group conductive lines electrically coupling to a second group of multiple vertical structures. The second group of multiple vertical structures is different from the first group of multiple vertical structures. The first group conductive lines are vertically spaced apart from one end of the multiple vertical structures, and the second group conductive line are vertically spaced apart from an opposite end of the nmultiple vertical structures. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11574921-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I728815-B |
priorityDate |
2018-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |