| abstract |
This article describes an integrated circuit device with an optimized fin critical size load. An exemplary integrated circuit device includes a core region of a first multi-fin structure and an input / output region including a second multi-fin structure. The first multiple fin structure has a first width, and the second multiple fin structure has a second width. The first width is larger than the second width. In some embodiments, the first multiple fin structure has a first fin interval, and the second multiple fin structure has a second fin interval. The first fin interval is smaller than the second fin interval. In some embodiments, the first adjacent fin pitch of the first multiple fin structure is greater than or equal to three times the minimum fin pitch, and the second adjacent fin segment of the second multiple fin structure The pitch is less than or equal to twice the pitch of the smallest fin. |