| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66477
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42372
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-45
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28556 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2017-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bc154fce90be4cf9dfe36d2bdefda3eb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0eed4044f333059f927dd5d92d14c9f2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ca8be91223a4d492826b8724fcd081cd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2c9b5034378b92ab568b7915a56b059c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_014e687705bcc4854c5d9353b765ccd2 |
| publicationDate |
2019-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I662619-B |
| titleOfInvention |
Semiconductor element, manufacturing method thereof and method of forming gate structure |
| abstract |
An embodiment of the present invention provides a field effect transistor including a channel layer and a metal gate structure formed of a semiconductor. The metal gate structure includes a gate dielectric layer; a barrier layer formed on the gate dielectric layer; a work function adjustment layer formed on the barrier layer and formed of one of Al and TiAl; a barrier layer Is formed on the work function adjustment layer and is formed of TiN; a bulk metal layer is formed on the barrier layer and is formed of W; a gate length above the channel layer is 5nm to 15nm, and the first A conductive layer has a thickness of 0.2 nm to 3.0 nm. The range between the maximum thickness and the minimum thickness of the first conductive layer is greater than 0% of the average thickness of the first conductive layer and less than 10% of the average thickness of the first conductive layer. |
| priorityDate |
2016-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |