http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I661492-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_31da94917d1067c89f7e22444c88a836 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4238 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2018-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2019-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_86c7fd17de89de48a59d7324762bfca6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d2515e3a577c70464806f2dd68515233 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b3412cffaee5b3bbd9ec22be151e5c59 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_232c14d7a5b51913cc488701e4fc05d5 |
| publicationDate | 2019-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-I661492-B |
| titleOfInvention | Method of forming a vertical field effect transistor having a self-aligned gate and a gate extension and the resulting structure |
| abstract | A method for forming an integrated circuit (IC) including (eg, in a VFET array) a plurality of vertical field effect transistors (VFETs) is disclosed herein. In this method, the self-aligned gates of each pair of VFETs and the self-aligned gate extensions contacting the self-aligned gates are formed substantially simultaneously, so that the gates surround a pair of semiconductor fins (end-to-end And the gate extensions fill the space between adjacent ends of the semiconductor fins. By forming a self-aligned gate and a self-aligned gate extension of a pair of VFETs, this method avoids the need to lithographically pattern the extended cut isolation regions between adjacent pairs of VFETs in a VFET array. Therefore, the method can implement a VFET array design with reduced fin pitch without causing defects such as those caused by stacking errors. The integrated circuit formed according to this method is also disclosed in this article. |
| priorityDate | 2017-09-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.