| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42376
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-535
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4991
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4958
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3081 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52 |
| filingDate |
2017-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-05-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9ea114d183933f7f93b174f97ce17a8f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_382ef30e3bb9ab74d2ca262ac72f5203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9642cc853b2594f51d516ecb962eeb13 |
| publicationDate |
2019-05-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I659514-B |
| titleOfInvention |
Semiconductor device and method of manufacturing same |
| abstract |
A method for manufacturing a semiconductor device (for example, a fin-type field effect transistor) includes the steps of forming a gate structure having a first lateral width and forming a first interlayer opening above the gate structure. The first interlayer opening has an uppermost surface at the bottom exposing the gate structure. The bottom of the first via opening has a second lateral width. The ratio of the second lateral width to the first lateral width is less than 1.1. A source / drain (S / D) region is laterally adjacent to the gate structure. A contact feature is disposed above the source / drain (S / D) region. A second interlayer opening extends to the uppermost surface of the contact feature and exposes the surface. The bottom of the second interlayer opening is disposed above the top of the gate structure. |
| priorityDate |
2016-08-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |