| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9047b16961c0aee78d7de367969339b2 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2245
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-2022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-1024
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-7208
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-7203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-60 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-061
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0679
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0246
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3459 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-06 |
| filingDate |
2016-03-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_56a7d76955b8d6599929ddff73b24fe5 |
| publicationDate |
2019-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I655538-B |
| titleOfInvention |
Semiconductor memory device and memory system |
| abstract |
Embodiments of the present invention provide a semiconductor memory device and a memory system capable of improving processing capabilities.nn n n A memory system according to an embodiment includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell array capable of storing first and second pages corresponding to the first and second bits; and first to third caches. The controller can send the second address signal corresponding to the second page before sending the first address signal corresponding to the first page, and the controller can also send the second address signal before sending the second address signal corresponding to the second page. The first address signal corresponding to page 1. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I700817-B |
| priorityDate |
2015-08-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |