http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I650742-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3287 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3243 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06G7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06G7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-32 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-20 |
| filingDate | 2015-03-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2019-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aa07e0c99c24a951a9ae29a1ca0eb12f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_21747acfb77b0d181ab4dff0d66658d4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_429b44bc1eaf4f40992c9a144121eb4c |
| publicationDate | 2019-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-I650742-B |
| titleOfInvention | Analog circuits, semiconductor devices, and electronic devices |
| abstract | An object of one embodiment of the present invention is to reduce power consumption of an analog operation circuit. An embodiment of the present invention is an analog operation circuit including a plurality of first circuits, wherein an output terminal of the k-th (k is a natural number) the first circuit is connected to an input terminal of the k + 1-th first circuit, Each of the first circuits includes a memory circuit that holds an analog signal, a second circuit that performs arithmetic processing using the analog signal, a switch that controls power supply to the second circuit, and a controller. The on-state of the included switch is controlled according to the controller included in the k + 1th first circuit, and the arithmetic processing performed in the second circuit included in the k + 1th first circuit. Start with the controller included in the k + 1th first circuit. |
| priorityDate | 2014-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 38.