| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_aea8583efc4aa4e2a9706d789804d37b |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0617
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0684
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76846
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76804
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32133 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11521 |
| filingDate |
2017-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bc6eb1706e541980e08a230d9f627f5e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_46149ea4aa2d6b674584317c1ec61258
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_adc31206895b716472e07e98caa04149
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5a96b091f80b5b4f0fea96f9df0d6324 |
| publicationDate |
2019-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I647821-B |
| titleOfInvention |
Integrated circuit of three-dimensional memory device with layered conductor and manufacturing method thereof |
| abstract |
An integrated circuit includes a multilayer stack and extending in the multilayer stacknA plurality of layered conductors, and the plurality of layered conductors extend into a conductor layer located below the multilayer stack. The layered conductor has a bottom conductive layer that makes ohmic electrical contact with the conductive layer in the substrate, and an intermediate conductive interface layer that is positioned above the bottom conductive layer and is cushioned at a portion of a side wall of the corresponding trench. And a top conductor layer over the top conductive interface layer. |
| priorityDate |
2017-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |