http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I647811-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1095 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41758 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-412 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-417 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 |
| filingDate | 2014-05-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2019-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_84baf87a2f5b71ef6647b0e091785205 |
| publicationDate | 2019-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-I647811-B |
| titleOfInvention | Semiconductor integrated circuit device |
| abstract | On the wafer for processing image information and the like, a logic circuit such as a digital signal processing circuit and a plurality of SRAMs are mixed. In this case, if it is 3 例如, for example, one 埠 is set to differential write & read 埠, and the other two 埠 are set to single-ended read 埠. However, in this configuration, although the occupied area of the embedded SRAM is small, the write & read 埠 is limited to one, and in the single-ended read, there is a clear high-speed read that cannot be expected as a differential read. The problem of characteristics. The outline of the present invention is in the memory cell structure of the embedded SRAM, and has three differential write & read ports, and a N well region is disposed in the center of the cell, for example, and a P well region is disposed on both sides of the center of the cell. |
| priorityDate | 2013-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 32.