| abstract |
A dynamic memory structure comprising a strip-shaped semiconductor material on a substrate, crossing a gate of a strip-shaped semiconductor material, and dividing the strip-shaped semiconductor material into a source terminal, a 汲 terminal, and a channel region, wherein a source width of the source terminal is greater than Or equal to the width of the channel region, at least a portion of the dielectric layer sandwiched between the gate and the strip of semiconductor material, and on the substrate, including a capacitor unit as the source terminal of the lower electrode. |