| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_31da94917d1067c89f7e22444c88a836 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0629
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02428
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823878
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-945
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-861
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1207 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76 |
| filingDate |
2013-08-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2ad660e3ec0662803c366754976cad26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_14bdf055c0068fdedc3638e84df40788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e62db9626f03308a7a35551a5d14dd51 |
| publicationDate |
2018-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I615978-B |
| titleOfInvention |
Semiconductor structure including semiconductor-on-insulator region and body region and method of forming the same |
| abstract |
A structure includes a semiconductor substrate, a semiconductor region on an insulator, and a body region. The semiconductor region on the insulator includes a first semiconductor region, a dielectric layer disposed between the semiconductor substrate and the first semiconductor region, and a first transistor including an active region disposed in the first semiconductor region. The dielectric layer provides electrical isolation of the first semiconductor region from the semiconductor substrate. The body region includes a second semiconductor region directly disposed on the semiconductor substrate. |
| priorityDate |
2012-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |