| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0865
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7825
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7823
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0922
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66734
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0882
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate |
2013-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b8f8d3b3e197bd09f0a44ff8286966ff |
| publicationDate |
2018-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I612665-B |
| titleOfInvention |
Semiconductor device and method of manufacturing the same |
| abstract |
The invention discloses a technology that can increase the withstand voltage near the end of a groove portion while suppressing an increase in contact resistance.nn n n The groove portion (GT) is provided in the semiconductor layer at least between the source offset region and the drain offset region in a plan view, and is provided in a source drain region from the source offset region to the drain offset region in a plan view. Direction. The gate insulating film GI covers the side and bottom surfaces of the groove portion GT. The gate electrode (GE) is provided in the groove portion (GT) at least in plan view, and is in contact with the gate insulating film (GI). The contact point GC is in contact with the gate electrode GE. Further, the contact GC is disposed in a plan view that is deviated from a first direction perpendicular to the source-drain direction with respect to a center line in the groove portion GT extending in the source-drain direction. Inside the slot GT. |
| priorityDate |
2012-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |