| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_33cf281df1fdf76b7da1bb88a75ba80d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136295 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-1343
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1288
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0248
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-124 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1368 |
| filingDate |
2009-06-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_08eba5ce6209bc9814eab8654b75e376
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ff739b840b70e441344d88011ee37b8e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_014ab5f6dc65e2da7aac8aab5897059b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2a7a878f0f6469eecc3fbd29750b083d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f60706eacb56f1a775cfedb10616e51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f2934a339d43022fece4b9ac187ab663
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3efa9856d5b7c103b5fbbbbd008014b2 |
| publicationDate |
2013-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I405017-B |
| titleOfInvention |
Array substrate of display device and manufacturing method thereof |
| abstract |
The array substrate has a gate electrode (103) of a thin film transistor (TFT), that is connected to the gate wiring formed on transparent substrate (101). A gate insulating layer (105) is formed on gate electrode, where the barrier metal layer (109) is formed between the source and drain electrodes (111a,111b) of TFT. The passivation film (115) is formed enclosing the TFT, gate and data wirings. A pixel electrode (123a) arranged on passivation film is made to contact drain electrode and barrier layer through a contact hole formed by etching the passivation film. An independent claim is included for fabrication method of array substrate of display device. |
| priorityDate |
2008-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |