http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I404063-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9a9aad45e5465bd5d3e7e503b2b16c65 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2227 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1057 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4093 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1084 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4074 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1066 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1051 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4076 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 |
| filingDate | 2008-10-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2013-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ce3b31cd8801d82fc1fa5f9adf5be546 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_481f64aa911c4ab568d01cc2ae56305c |
| publicationDate | 2013-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-I404063-B |
| titleOfInvention | Memory system and control method for memory |
| abstract | The memory system includes a semiconductor memory that has an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit coupled to the internal circuit and operates according to a second power supply voltage, a first control unit that includes a control input/output circuit, coupled to the memory input/output circuit and operates according to the second power supply voltage, a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal, a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal, and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit. |
| priorityDate | 2007-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 41.