Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_aea8583efc4aa4e2a9706d789804d37b |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0466 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42332 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7923 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7887 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
filingDate |
2005-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2007-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fc4b7361f918cb1e4340fac3b657feba |
publicationDate |
2007-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
TW-I291766-B |
titleOfInvention |
Charge trapping non-volatile memory and method for operating same |
abstract |
A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath gates in the plurality of gates. Circuitry to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7864594-B2 |
priorityDate |
2004-07-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |