| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fd83260a96356882b5f50dd097411a72 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0025 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03D13-004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-089
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-15
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-093 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-06 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-107
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-15
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-081
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-093
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-089
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-113
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03D13-00 |
| filingDate |
2004-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2007-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a8471adbce6fae548b78c27963ca71d |
| publicationDate |
2007-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I285025-B |
| titleOfInvention |
Clock and data recovery circuit |
| abstract |
This invention provides a clock and data recovery circuit capable of tracking frequency modulated input data. The clock and data recovery circuit includes: a phase detector for inputting a data signal and a synchronized clock signal, detecting phase retardation or advance, and outputting a UP1/DOWN1 signal; first and second integrators for integrating a UP1/DOWN1 signal and outputting UP2/DOWN2 and UP3/DOWN3 signals, respectively; a pattern generator for inputting the UP3/DOWN3 from the second integrator and outputting a UP4/DOWN4 signal; a mixer for inputting the UP2/DOWN2 signal from the first integrator and the UP4/DOWN4 signal from the pattern generator and then producing and outputting a UP5/DOWN5 signal; a phase interpolator for interpolating the phase of the input clock signal based on the UP5/DOWN5 from the mixer and then outputting; wherein the clock signal outputted from the phase interpolator is fed back and inputted to the phase detector as the clock. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9455725-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I555338-B |
| priorityDate |
2003-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |