| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4edd4e526605dbd18b513b4b30d19ab2 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-2011
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2330-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2330-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2320-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0408 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3275
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3648
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3688 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-133
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L51-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C19-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 |
| filingDate |
2004-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2007-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fa473a847b57889d4f5e89e836283634
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a2344486d91270987a2cb07f2767559 |
| publicationDate |
2007-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I271698-B |
| titleOfInvention |
Display device |
| abstract |
This invention provides a display device capable of suppressing the deterioration of image. The display device of this invention has a shift register circuit 4a1 including an output side circuit 4c1. The output side circuit contains a p channel transistor PT1 connected to a negative potential side HVSS and being turned on in response to a clock signal HCLK1, a p channel transistor PT2 connected to a positive potential side HVDD, a p channel transistor PT3 connected between the gate of the P channel transistor PT1 and the positive potential HVDD, and a high resistance value resistor R1 having a resistance value of about 100 KOmega connected between the gate of the p channel transistor PT1 and a clock signal line for supplying a clock signal HCLK1. |
| priorityDate |
2003-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |