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filingDate 2005-03-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2006-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9462533ba2d39b578178049a49711d6a
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publicationDate 2006-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-I267930-B
titleOfInvention Interconnect and method of fabricating the same
abstract A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a firs copper layer is deposited by a first ECP process at a 10 mA/cm<2> current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes an H, plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm<2> current density and second deposition step at a 60 mA/cm<2> current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Re performance are achieved by this method.
priorityDate 2004-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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