http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I262400-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a71b813ebb799d255ef4e8b6d39583d0 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-7867 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-76 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38 |
| filingDate | 2002-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2006-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1dc56e7e957361fe89ddbf52e8eee738 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ce024be11ce059f3c490186043c9e1f3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_456d307d4df88fc2bcf129d7ec63540b |
| publicationDate | 2006-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-I262400-B |
| titleOfInvention | Apparatus, system, and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements |
| abstract | The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes. |
| priorityDate | 2001-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.