http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I248172-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b91cf5402e7347f4863d03a24805eb2d |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8249 |
| filingDate | 2004-07-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2006-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_487e1faeff22c85e222e3a08c61adbbf |
| publicationDate | 2006-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-I248172-B |
| titleOfInvention | Self-aligned trench DMOS transistor structure and its manufacturing methods |
| abstract | A self-aligned trench DMOS transistor structure of the present invention comprises a self-aligned source structure and a self-aligned trench gate structure, in which the self-aligned source structure comprises a p- base diffusion region, a self-aligned n+ source diffusion ring, a self-aligned p+ contact diffusion region, and a self-aligned source contact window; the self-aligned trench gate structure comprises a self-aligned silicided conductive gate structure, a self-aligned polycided conductive gate structure, or a self-aligned polycided trenched conductive gate structure. The self-aligned trench DMOS transistor structure as described is fabricated by using only one masking photoresist step and can be scaled down to get a high-density trench DMOS power transistor with ultra low on-resistance, low parasitic gate-interconnect resistance, and high device ruggedness. |
| priorityDate | 2004-07-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 41.