http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I247382-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c5520dd38cc403678d9f91e0b0ee95fb |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-927 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-43 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 2002-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2006-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f1b2068ef3b7b6001a8397a2cab92f57 |
| publicationDate | 2006-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-I247382-B |
| titleOfInvention | Method for manufacturing a semiconductor device |
| abstract | A method for manufacturing a semiconductor device comprises: (a) forming a dummy gate provided with a sidewall spacer at its side wall and an anti-silicidation film thereon on a semiconductor substrate, as well as forming a source/drain region on the surface of the semiconductor substrate; (b) forming a metal film on the whole surface of the obtained semiconductor substrate, the resultant being subject to a silicide reaction to form a silicide layer only on the source/drain region; (c) forming an interlayer dielectric film on the obtained substrate, the surface of the interlayer dielectric film being removed until the anti-silicidation film is exposed; (d) removing the anti-silicidation film and the dummy gate to form a trench in the interlayer dielectric film; and (e) laminating a gate insulating film and gate electrode material film in the trench, the gate insulating film and gate electrode material film being removed until the surface of the interlayer dielectric film is exposed to form a gate electrode and gate insulating film in the trench. |
| priorityDate | 2001-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 57.