Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4edd4e526605dbd18b513b4b30d19ab2 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0267 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3677 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3688 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0275 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3266 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3275 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-184 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28 |
classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-32 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L51-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C19-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C19-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0175 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C19-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-133 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-20 |
filingDate |
2004-05-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2005-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fa473a847b57889d4f5e89e836283634 |
publicationDate |
2005-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
TW-I246050-B |
titleOfInvention |
Display device |
abstract |
A display device capable of suppressing the reduction of the scanning characteristics is provided. The display device has a shift register circuit (4a1) constituted by connecting a plurality of first circuit parts (4b1), the first circuit part (4b1) including a p-channel transistor (PT1) connected to a negative side potential HVSS and turning ON in response to a clock signal HCLK1, a p-channel transistor (PT2) connected to a positive side potential HVDD, and a p-channel transistor (PT3) connected between the gate of the p-channel transistor (PT1) and the positive side potential HVDD and having two gate electrodes (91) and (92) electrically connected to each other. |
priorityDate |
2003-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |