| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_eda542721b5af3c5a47c4af1095cc831 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-10253
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-09701
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-12042
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01078
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48137
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48247 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-4334
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49575 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-495
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-433 |
| filingDate |
2003-11-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2005-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d71b6ed1382ef9cb32574120b8cf8723
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_72b0c84e29524cc89f2a9b429672ab9a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eb38e9a15d7478cf2347962615c216f3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dcbe77d330e3cde1e9c894e0321ae783 |
| publicationDate |
2005-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I236741-B |
| titleOfInvention |
Chip package and substrate |
| abstract |
A chip package includes a substrate, a lead frame, a chip, wire-bonding wires, a heat sink and molding compound. The substrate has a first metal layer, a second metal layer and a conductor. The first metal layer is positioned on a first surface of the substrate. The second metal layer is positioned on a second surface of the substrate. The conductor is positioned on a lateral surface of the substrate. The lead frame is positioned on the first surface of the substrate and is electrically connected with the first metal layer. The chip has back surface mounted on the lead frame or on the first surface of the substrate. The wire-bonding wires connect the chip to the lead frame. The heat sink is mounted on the second surface of the substrate and is electrically connected with the second metal layer. The molding compound envelops the chip, the wire-bonding wires and the lead frame. |
| priorityDate |
2003-11-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |