http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I231938-B

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_203d2357418e846eb9d27bca66014f81
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-24
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-10
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-18
filingDate 2002-07-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2005-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6c0d8b38c4388d5ea5488727b8d4f18f
publicationDate 2005-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-I231938-B
titleOfInvention Bit line decoding scheme and circuit for dual bit memory with a dual bit selection
abstract In the present invention a bit line decoder scheme is described that connects data and voltage to a plurality of bit lines of a dual bit flash memory array. The bit lines are connected to a plurality of intermediate data lines by a first decoder unit and the intermediate data lines are connected to a plurality of data lines of the sense amplifiers by a second decoder unit. In one embodiment the voltage is connected to a selected bit line through a separate decoder unit and in a second embodiment the voltage is connected through the decoder unit connected to the intermediate data lines.
priorityDate 2001-07-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 24.