http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-591747-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fd83260a96356882b5f50dd097411a72 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76838 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2003-03-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2004-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4e6f44bd987ba24f7638001865ec7093 |
| publicationDate | 2004-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-591747-B |
| titleOfInvention | Method of fabricating semiconductor device |
| abstract | A method of fabricating a semiconductor device, including at least the steps of (a) forming a via-hole or trench throughout an electrically insulating layer (3), (b) forming a wiring material layer (5a) on the electrically insulating layer (3) such that the via-hole or trench is filled with the wiring material layer (5a), (c) annealing the wiring material layer (5a), and (e) applying chemical mechanical polishing (CMP) to the wiring material layer (5a) such that the wiring material layer (5a) exists only in the via-hole or trench, characterized by (d) cooling the wiring material layer (5a) down to a temperature equal to or lower than a room temperature. The step (c) is carried out prior to the step (e), and the step (d) is carried out after the step (c). |
| priorityDate | 2002-03-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.