http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-560068-B

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_77143a57bdb61a1a0b7826425e55474d
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
filingDate 2002-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2003-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_72307e2f84c1c19953d3e19c471dffa1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_562c0a6adcd37186a9b37f5373c60609
publicationDate 2003-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-560068-B
titleOfInvention Nonvolatile memory cell, operating method of the same and nonvolatile memory array
abstract The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array. A p-well 101 is formed in a surface of a substrate 10 and a channel forming semiconductor region 110 is defined in a surface of the p-well 101 and separated by a first n+ region 121 and a second n+ region 122. A carrier-supplying portion (CS: carrier supply) 111 is formed coming into contact with the first n+ region 121 and a carrier-acceleration-injection portion 112 (AI: acceleration and injection) is in contact with the second n+ region 122 in the channel forming semiconductor region 110 wherein the carrier-supplying portion 111 and carrier-acceleration-injection portion 112 are in contact with each other.
priorityDate 2002-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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