http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-548703-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fd83260a96356882b5f50dd097411a72 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2002-07-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2003-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d157b4a296300d9d97794a91468867d5 |
| publicationDate | 2003-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-548703-B |
| titleOfInvention | Manufacturing method of semiconductor device |
| abstract | The present invention relates to a method of manufacturing a semiconductor device which has an isolation region with a trench isolation structure, comprising a trench formed on a semiconductor substrate and a buried insulating film buried within said trench; which comprises the steps of: forming a gate electrode in an active region adjacent to said isolation region on said semiconductor substrate; applying an ion implantation onto said semiconductor substrate using said gate electrode as a mask to form a first dopant diffusion region which is to be used as a LDD region; forming a first insulating film and a second insulating film, in this order, on the entire surface of a principal plane of said semiconductor substrate, inclusive of said gate electrode; performing an etch back, using said first insulating film as an etching stopper, to form a first sidewall of said second insulating film on a lateral face of said gate electrode, with said first insulating film lying therebetween; etching said first insulating film by an entire surface etch back to form a second sidewall of said first insulating film on the lateral face of said gate electrode; making another ion implantation, using said gate electrode as well as said first and said second sidewall as a mask, to form a second dopant diffusion region which is to be used as a source/drain region; forming an interlayer insulating film on the entire surface of the principal plane of said semiconductor substrate; and forming a contact hole to reach said second dopant diffusion region from the top surface of said interlayer insulating film. The present invention can suppress well the leakage between the contact and the substrate because, even if a contact hole is formed overlapping an element isolation region, the drop of the buried insulating film lying within the trench can be well prevented or suppressed. |
| priorityDate | 2001-07-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
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