http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-548544-B
Outgoing Links
Predicate | Object |
---|---|
assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f58e0f35558e8d8a3a745786bd7dd4d5 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-22 |
filingDate | 2001-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate | 2003-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0c86ec319cd8f4b809005e5390e5414a |
publicationDate | 2003-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | TW-548544-B |
titleOfInvention | Method for single-step interruption debug for PCI bus cycle and the device thereof |
abstract | The present invention provides a method for single-step interruption debug for PCI bus cycle and the device thereof, which uses the control on IRDY# signal during the dummy bus master cycle (false or irregular bus master cycle), and further includes the function of single-step interruption debug by individually displaying ADDRESS, data, COMMAND, and BE# signal states in each cycle on a display device through the respective buffers. |
isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-100388227-C http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-100362485-C http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-100373348-C |
priorityDate | 2001-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 20.