http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-546829-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b8c08f5aa538ae9419359e8ee68ca47c |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate | 2002-05-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2003-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d1561ce25db169ea5766bbc3119fc6a9 |
| publicationDate | 2003-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-546829-B |
| titleOfInvention | Manufacturing method of self-aligned floating gate EEPROM |
| abstract | The present invention provides a manufacturing method of self-aligned floating gate EEPROM (electrically erasable programmable read only memory), which comprises: firstly providing a semiconductor substrate with a long-strap-like hard mask, and using the hard mask as the shielding object to etch the semiconductor substrate to form a trench; forming oxide whose upper surface is of the same height as that of the hard mask; removing the hard mask, so as to form a recess between the oxide filled into the trench; next, globally depositing a first polysilicon layer to fill into the recess, planarizing the first polysilicon layer, so as to form a long-strap-like first polysilicon whose upper surface has the same height as that of the upper surface of the said oxide in the first direction; and selectively etching the long-strap-like first polysilicon to form a floating gate block, and exposing part of the semiconductor substrate. |
| priorityDate | 2002-05-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.