http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-527725-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b91cf5402e7347f4863d03a24805eb2d |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate | 2002-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2003-04-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_487e1faeff22c85e222e3a08c61adbbf |
| publicationDate | 2003-04-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-527725-B |
| titleOfInvention | A scalable dual-bit flash memory cell and its contactless flash memory array |
| abstract | A scalable dual-bit flash memory cell of the present invention comprises a scalable gate region having a pair of floating-gate structures with a select-gate region being formed therebetween and a planarized control/select-gate over a second gate-dielectric layer being formed over the pair of floating-gate structures with or without a pair of second sidewall dielectric spacers being formed over a pair of floating-gates; a conductive bit-line together with a first sidewall dielectric spacer being formed over a flat bed formed by a common-source/drain diffusion region and etched raised field-oxide layers. A contactless dual-bit flash memory array of the present invention comprises a plurality of conductive bit-lines being formed transversely to a plurality of parallel STI regions and a plurality of word lines integrated with a plurality of control-gates of the described cells being patterned and formed transversely to the plurality of conductive bit-lines. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7799638-B2 |
| priorityDate | 2002-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 45.