| abstract |
This invention provides a semiconductor memory device, which can reduce parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them. In the above-mentioned semiconductor memory device, second complementary global bit lines (GBL, /GBL) for transmitting data read out of memory cells MC via complementary bit lines (BL, /BL) are arranged above a memory cell array (block). Meanwhile, each second global bit line (GBL or /GBL) is so arranged to have an isosceles triangle with the center of the section of one (BL) of the complementary bit lines (BL, /BL), the center of the section of the other (/BL), and the center of the section of the second global bit line (GBL or /GBL) arranged directly above these complementary bit lines (BL, /BL) as its vertexes. |