| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_339b520223c56ad4e2c657929769d8ff
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_cdf56bffa35b8aca1af392bf6df568f1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0416
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-846
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-22 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02 |
| filingDate |
2001-08-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2003-03-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2c87226417bd9ab631df70e2455361c4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c2c52adb147e5c1997f5253f05c94a31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_307ebe9535092f2358cab9ff3633f9e3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f91d5429b5cdca01ef6c9462eb93db8a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2c3bf65ae77eb81f325ff14c0e9de4fa |
| publicationDate |
2003-03-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-523751-B |
| titleOfInvention |
Nonvolatile semiconductor memory and automatic erasing/writing method thereof |
| abstract |
There is provided a nonvolatile semiconductor memory comprising: a memory bock composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and means for updating a content of the register by a data processor coupled to the register. By using this updating means to update the content of the register, the memory decoder and the charge pump are controlled, the data of the memory block is erased, and data is written in/read from the nonvolatile transistor. Thus, selecting means other than a laser can be applied for suppressing the increase of an LSI circuit size in the same chip as that for a dedicated control circuit, verifying the disconnected state of a FUSE circuit in the memory, and trimming the FUSE circuit. |
| priorityDate |
2001-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |