http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-521398-B

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306
filingDate 2002-01-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2003-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a708cb20e0e4e2abce0b27b65c2b7dfe
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publicationDate 2003-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-521398-B
titleOfInvention Process of integrating capacitance-use groove with removal of black silicon
abstract A process of integrating capacitance-use groove with removal of black silicon comprises: forming an etching mask on a semiconductor substrate; using the etching mask as a shield and etching the semiconductor substrate to form a capacitance-use groove with a specified depth; forming a thermal oxidation layer on the surface of the capacitance-use groove; forming a sacrificial layer on the surface of the semiconductor substrate of the memory unit region in which the sacrificial layer fills in the capacitance-use groove formed with the thermal oxidation layer; using the sacrificial layer to shield the memory unit region and removing the tip structure of the black silicon; removing a portion of the sacrificial layer to expose the surface of the thermal oxidation layer on the upper part of the groove and leaving the sacrificial layer on the lower part of the groove; using the sacrificial structure as a protective article and removing the exposed thermal oxidation layer; and removing the remaining sacrificial structure.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103227100-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I475665-B
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type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 25.