http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-513796-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b91cf5402e7347f4863d03a24805eb2d |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-00 |
| filingDate | 2001-01-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2002-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_487e1faeff22c85e222e3a08c61adbbf |
| publicationDate | 2002-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-513796-B |
| titleOfInvention | A scalable stacked gate flash memory device and the manufacturing method of high-density array |
| abstract | A scalable stacked-gate flash memory device and the manufacturing method of high-density array are provided. It utilizes four kinds of spacer technologies to produce a scalable stacked-gate flash memory device. The first spacer technology is used to form a buffering oxide spacer to be the channel stop of STI (shallow trench isolation) implantation without sacrificing the width of active region of the non-volatile memory device during oxidizing the etched surface of the shallow trench. The second spacer technology uses a shallow trench isolation method to produce a self-aligned floating gate whose coupling ratio can be largely modulated and then the external control voltage for writing and erasing can be reduced. The third spacer technology is used to define the gate length of the scalable stacked-gate structure. The fourth spacer technology is used to form sidewall spacers for ion implantation of self-aligned source/drain diffusion region, salicide formation of the self-aligned source/drain diffusion areas or the common buried source area and self-aligned contact formation. The scalability of this invention is that the channel length of the stacked-gate flash memory device can be modulated to let the minimum length smaller than the applying technology and let the existing different types of flash memory structure, such as NOR and NAND to obtain the high-density stacked-gate flash memory device array. Accordingly, the scalable stacked-gate flash memory device can be used to manufacture the high-density, high-speed, low-voltage and low-power flash memory array and system required by massive storage applications. |
| priorityDate | 2001-01-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 77.