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filingDate 2000-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2002-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd2804f01b529d8d2a16b939c2a681fb
publicationDate 2002-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-508579-B
titleOfInvention Burst mode flash memory
abstract A clock generator circuit in response to an external output enable signal generates an internal clock signal that is delayed to increase the reliability of the data outputted from the flash memory. A clock trigger generator circuit by decoding address signals generates an internal clock signal to reduce the latency time of the output of data with respect to the external clock signal. A bypass signal is provided to disable the clock trigger generator circuit. An output circuit provides a bypass data path to additionally reduce the latency time of the outputting of data for a burst mode flash memory. A decoder counter selector circuit provides a ""look-ahead"" address decoding scheme to reduce the time needed to output data.
priorityDate 1999-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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