| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9d527f9a5c3e991a1797de3518a88d14 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-3181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-3004 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3181 |
| filingDate |
2001-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2002-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2cf55acfe6aab743f5ef33c08756d0b0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_554cf895c0eade9c3ef7b733ba449410
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4c6aed19bd0be1c727988177014b94fe |
| publicationDate |
2002-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-500926-B |
| titleOfInvention |
Failure analysis method and apparatus for semiconductor integrated circuit |
| abstract |
The present invention provides a kind of failure analysis method and failure analysis apparatus capable of greatly improving failure analysis reliability for semiconductor integrated circuit. In the invention, after the test pattern array with plural test patterns is sent to the semiconductor integrated circuit, some analysis portions, which can generate voltage change corresponding to the variations of the supplied test patterns, are stored in accordance with the test pattern array. Then the transient power source current generated due to the variations of the test patterns in the semiconductor circuit is measured and is checked to determine whether the measured transient power source current is normal or not. Then, based on the test pattern array which has the indication of abnormal transient power source current, and the analysis portion which is stored corresponding to the test pattern array, the failure portion in the semiconductor integrated circuit is determined. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11047906-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10444278-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11353479-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10209274-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11448689-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103116121-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103116121-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110031744-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10191111-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I593983-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10379154-B2 |
| priorityDate |
2000-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |