http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-495982-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-783 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78615 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 2001-03-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2002-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d27d2b45becd6e95c5522002c80c18a4 |
| publicationDate | 2002-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-495982-B |
| titleOfInvention | Semiconductor device |
| abstract | In an isolation region of an SOI substrate (1), an STI (10) is formed in a silicon layer (4). In an end portion of the isolation region, a p<SP>+</SP>-type impurity diffusion region (11) is selectively formed, being buried in part of an upper surface of the STI (10), in an upper surface of the silicon layer (4). In an element formation region of the SOI substrate (1), a body region (15) which is in contact with a side surface of the impurity diffusion region (11) is formed in the silicon layer (4). A tungsten plug (14) is in contact with the impurity diffusion region (11) with a barrier film (13) interposed therebetween, and in contact with part of an upper surface of a gate electrode (9) and a side surface thereof with the barrier film (13) interposed therebetween. With this structure obtained is a semiconductor device which makes it possible to avoid or suppress generation of an area penalty which is generated when a gate-body contact region is formed inside the silicon layer in an SOI-DTMOSFET. |
| priorityDate | 2000-07-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.