http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-483058-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 1998-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2002-04-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_495c6166d537cbce3f0a7d872f5e633d |
| publicationDate | 2002-04-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-483058-B |
| titleOfInvention | Manufacture method of self-aligned silicide |
| abstract | This invention provides a manufacture method of self-aligned silicide (salicide), which includes: constructing a first conduction type metal-oxide-semiconductor (MOS), a second conduction type MOS, wiring lines of the first conductive type MOS and the second conduction type MOS on a semiconductor substrate; selectively depositing a undoped polysilicon layer; using resist layer as mask to cover the first conduction type MOS and the second conduction type MOS; selectively implanting a second conduction type dopant and a first conduction type dopant in low energy and high dose condition; depositing metal on the doped polysilicon surface; and utilizing rapid thermal process to form metal silicide between the metal layer and the polysilicon layer. This method is not only suitable for complementary MOS (CMOS) structure but also reduces sheet resistance of source/drain regions and prevents the occurrence of leakage current from junction penetration. |
| priorityDate | 1998-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.