| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0411
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-104
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1072 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1068
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1008 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C17-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-42 |
| filingDate |
2000-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2002-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3ebbfdaf3046d4a2ed461939c100fa04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5f2e882ad1768c13fe60352030edcd06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_57379487688de04a69d364f1c6f138d2 |
| publicationDate |
2002-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-473719-B |
| titleOfInvention |
Flash memory |
| abstract |
A flash memory of the present invention has internal automatic execution of error correction which is exchangeable with the flash memory without built-in error correction circuit. It comprises the following parts: a memory sector, a command interface 3 which receives the external command to generate the control signal, a circuit 7 to generate the control signal according to the write-in command signal for initilization; an error correction circuit 11 initialized according to the write-in data input command signal, which receives the externally inputted write-in data synchronously with the externally inputted first signal, and is initialized according to the write-in command to generate the examining data synchronously with the control signal; a temporary memory circuit 17 installed for each memory cell, which is loaded with the write-in data and the examining data; and the write-in circuit 13, 14, 15 initialized according to the write-in command to write the memorized write-in data and the examining data into the memory region. |
| priorityDate |
1999-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |