http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-473716-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-21 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-405 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-21 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C14-00 |
| filingDate | 2000-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2002-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d5d40abbb880bdaf962645c402c15a36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_55bb94c868c3c9ea88f24656080f05e3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e161dbe38cb174385034592f7d75521b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_42887316ad8f1a42b3a3492a9541105e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c6409a5e15ec043eca28680ffc7f17ba |
| publicationDate | 2002-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-473716-B |
| titleOfInvention | Ferroelectric memory and semiconductor memory |
| abstract | The purpose of the present invention is to inhibit the decrease in the accumulated charge of polarization in the memory cell and the occurrence of disturb during read/write operations for a chain type ferroelectric memory (FRAM). The present invention has a memory cell unit comprising: ferroelectric memory cells (M0-M7) electrically connected in series to each other, a plate line (PL0) connected to an electrode of the memory cell unit, a bit line (BL) connected to the other electrode of the memory cell unit via a switching transistor (QB0), a sense amplifier (SA) which amplifies the voltages of this bit line and its complementary bit line BBL, and a transistor (QS) inserted between the switching transistor and the sense amplifier, and that a value (VPP1) which is the minimum value of the gate voltage in the transistor (QS) obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value (VPP2) which is the maximum value of the gate voltage in the transistor (QS) obtained during falling of the plate line voltage and comparative amplification. |
| priorityDate | 1999-06-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 46.