http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-469374-B
Outgoing Links
Predicate | Object |
---|---|
assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_17ff64581f65171a59e5e6afbaa65b1b http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a |
classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1605 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-30 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-36 |
filingDate | 1999-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate | 2001-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2e0f1b179595b4fbe907417b6730f017 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e3eeccaeaeddac70854df48e513e1c57 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f14fd3ae83d36ad0bcc518229ff35301 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9dfc96db65d1a10467fea43ba58e0e8f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1a9e64607ef02f0a75b2f80c08b65ad9 |
publicationDate | 2001-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | TW-469374-B |
titleOfInvention | A data streamer |
abstract | In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus. |
priorityDate | 1998-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 206.