http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-459345-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2000-11-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2001-10-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_32e386d600337f8e34c642452de3e3bb |
| publicationDate | 2001-10-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-459345-B |
| titleOfInvention | Forming method for borderless contact |
| abstract | A forming method for borderless contact which includes the following steps: providing a silicon substrate and forming a plurality of shallow trenches filled up with silicon dioxide in the substrate so as to define an active area between each pair of shallow trenches; then, forming a gate oxide on the active area; forming a polysilicon gate on the gate oxide and a lightly doped drain area in each side of the polysilicon gate in the substrate; next, forming a silicon nitride spacer on each sidewall of the polysilicon gate; removing the silicon dioxide at each corner of the shallow trench and forming a corner trench at each corner of the shallow trenches near one side of the active area; then, forming a thin layer of silicon dioxide on the polysilicon gate and the active area as the stop layer; forming a polysilicon layer on the entire substrate; conducting the back etching until the stop layer and forming polysilicon residual in the corner trench; next, using the thermal oxidation method to form a shielding oxide on top of the polysilicon gate, the active area and the corner trench; then, forming a heavily doped drain/source on one side of each lightly doped drain area; removing the shielding oxide to conduct the process of self-aligned metal silicide for forming a self-aligned metal silicide on the polysilicon gate, the active area and the corner trench; then, forming an inter-layer dielectric on the entire substrate and conducting planarization; finally, forming a borderless contact in the inter-layer dielectric and exposing part of the self-aligned metal silicide layer on a drain/source. |
| priorityDate | 2000-11-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.