| abstract |
Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an inhibit and select segmentation scheme; (2) a multilevel memory decoding scheme, a feedthrough-to-memory decoding scheme, a feedthrough-to-driver decoding scheme, and a winner-take-all Kelvin memory decoding scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a positional linear reference system, a positional geometric reference system, and a geometric compensation reference system. The apparatus and method enable multilevel programming, reading, and margining. |