http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-455956-B

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bc905cbef116a1ec61d12125af9427f3
classificationCPCAdditional http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-05
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60
filingDate 1999-10-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2001-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2bea6c8888cf85a8286b70640420368b
publicationDate 2001-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-455956-B
titleOfInvention Barrier layer used in bonding pad of Cu chip
abstract There is provided a method of barrier layer used in the bonding pad of Cu chip, wherein the barrier layer is located between the bonding pad and the metal cap. In the conventional skill, a reliability problem is encountered between the bonding pad and the metal cap. The present invention provides a method for solving the problem, which comprises forming an interlayer dielectric on the integrated circuit structure, wherein the interlayer dielectric includes a metal bonding pad; next, sequentially forming a barrier layer and a passivation layer on the interlayer dielectric and the metal bonding pad; after transferring the pattern of the barrier layer and the bonding pad layer, forming a passivation layer on the interlayer dielectric and the metal passivation layer; and forming a bonding pad opening after transferring the passivation layer pattern. In the present invention, the sequence of forming the passivation layer and the barrier layer can be exchanged.
priorityDate 1999-10-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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