http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-454282-B
Outgoing Links
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|---|---|
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| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2886 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-00 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-32 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R1-073 |
| filingDate | 2000-05-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2001-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b9c9254f4c609b7304da9d35afa76346 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7b7e811f9f195250c6faa42e85db76f4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f28b31ee17700fdc0d529e959f853a69 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_98671fe4f188ebc668d12e099dd2577c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f1c0428f9d22441464dde874a1826e68 |
| publicationDate | 2001-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-454282-B |
| titleOfInvention | Probe card and method of testing wafer having a plurality of semiconductor devices |
| abstract | A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board. Displacements of the internal terminal resulting from the temperature load applied during testing of the wafer are compensated by the level transitioning portion of the first wiring. Unevenness involved with the contact between the contact electrodes on the probe card and the electrodes on the chips are compensated by the contact electrodes and/or elastic material according to the present invention. An electrode pitch of the contact electrodes is expanded by the first wiring. |
| priorityDate | 1999-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID5461123 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419559541 |
Total number of triples: 34.