http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-451447-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1288 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-458 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-124 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136286 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-1362 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1362 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-84 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-77 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-45 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1368 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-136 |
| filingDate | 2000-08-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2001-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_596230023fdcebcd2b0b14c5ded3489f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7e8895c19224c221fae0bb885f21f44a |
| publicationDate | 2001-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-451447-B |
| titleOfInvention | Contact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the same |
| abstract | First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited an patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pad and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed. Next, IZO is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively and electrically connected to the drain electrode, the gate pad and the data pad via the inter-layer reaction layers. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I479692-B |
| priorityDate | 1999-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 33.