http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-451312-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d76a119c7cd6056b28cc860aa47db4c0 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-265 |
| filingDate | 2000-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2001-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a1123b4cb0962f23361c9632f9b97293 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_86b9b71fc0c538ee9da6f2d180c69da8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_33d9aa6e4643fbca3e484aa5c2131155 |
| publicationDate | 2001-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-451312-B |
| titleOfInvention | Manufacture method for sheet resistor of modified concave power semiconductor |
| abstract | This invention describes manufacture method of a power transistor device, which utilizes ion capable of self-aligned onto field oxide implanted well, substrate, drain and source to fabricate semiconductor device with good symmetry. Sheet resistance of the device can also be reduced by increasing the silicon concentration beneath the gate so that effectiveness of power semiconductor device can be improved. The inventive manufacture method includes at least: the first epitaxial silicon layer being formed on a n-type silicon substrate, an oxide layer and a silicon nitride layer being formed on the epitaxial silicon layer, the position of gate being defined using a mask and part of the oxide layer and the silicon nitride layer being etched, using conventional ion implant method to lightly dope n-type impurity into the gate area of the epitaxial silicon layer, sheet resistance being reduce by driving the n-type dopant though thermal diffusion into the epitaxial silicon layer using a furnace and also growing field oxide area at the gate position at high temperature, removing the silicon nitride underneath field oxide area at the gate position and forming substrate area by driving ion at self-aligned field oxide area, forming source by driving ion into epitaxial layer after the center of the substrate area being patterned and mask aligned, removing mask layer and field oxide layer and depositing another oxide layer and polysilicon layer, using another mask to define gate area and etch, and forming passivation layer, contact and conductive connect. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I452633-B |
| priorityDate | 2000-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.